Renesas HD6417641 Network Card User Manual


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Section 1 Overview
Rev. 4.00 Sep. 14, 2005 Page 4 of 828
REJ09B0023-0400
Items Specification
Bus state controller
(BSC)
Physical address space divided into eight areas, four areas (area 0,
areas 2 to 4), each a maximum of 64 Mbytes and other four areas
(areas 5A, 5B, areas 6A, 6B), each a maximum of 32 Mbytes
The following features settable for each area independently
Bus size (8, 16, or 32 bits), but different support size by each areas
Number of wait cycles (wait read/write settable independently area
exists)
Idle wait cycles (same area/another area)
Specifying the memory to be connected to each area enables
direct connection to SRAM, SDRAM, Burst ROM, address/data
MPX mode supporting area exists
Outputs chip select signal (CS0, CS2 to CS4, CS5A/B, CS6A/B)
for corresponding area (selectable for programming CS
assert/negate timing)
SDRAM refresh function
Supports auto-refresh and self-refresh mode
SDRAM burst access function
Area 2/3 enables connection to different SDRAM (size/latency)
Direct memory access
controller (DMAC)
Number of channels: four channels (two channels can accept external
requests)
Two types of bus modes
Cycle steal mode and burst mode
Interrupt can be requested to the CPU at completion of data transfer
Supports intermittent mode (16/64 cycles)
User debugging
interface (H-UDI)
E10A emulator support
JTAG-standard pin assignment
Realtime branch trace