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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 275 of 982
REJ09B0023-0400
12.3.3 Address Map
The external address space has a capacity of 384 Mbytes and is used by dividing 8 partial spaces.
The kind of memory to be connected and the data bus width are specified in each partial space.
The address map for the external address space is listed below.
Table 12.2 Address Space Map 1 (CMNCR.MAP = 0)
Physical Address Area Memory to be Connected Capacity
H'00000000 to H'03FFFFFF Area 0 Normal memory
Burst ROM (asynchronous)
Burst ROM (synchronous)
64 Mbytes
H'04000000 to H'07FFFFFF Area 1 Internal I/O register area*
2
64 Mbytes
H'08000000 to H'0BFFFFFF Area 2 Normal memory
Byte-selection SRAM
SDRAM
64 Mbytes
H'0C000000 to H'0FFFFFFF Area 3 Normal memory
Byte-selection SRAM
SDRAM
64 Mbytes
H'10000000 to H'13FFFFFF Area 4 Normal memory
Byte-selection SRAM
Burst ROM (asynchronous)
64 Mbytes
H'14000000 to H'15FFFFFF Area 5A Normal memory 32 Mbytes
H'16000000 to H'17FFFFFF Area 5B Normal memory
Byte-selection SRAM
MPX-I/O
32 Mbytes
H'18000000 to H'19FFFFFF Area 6A Normal memory 32 Mbytes
H'1A000000 to H'1BFFFFFF Area 6B Normal memory
Byte-selection SRAM
MPX-I/O
32 Mbytes
H'1C000000 to H'1FFFFFFF Area 7 Reserved*
1
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
2. Access the address indicated in section 24, List of Registers, for the on-chip I/O register
in area 1. Do not access area 1 addresses which are not described in the register map.
Otherwise, the correct operation cannot be guaranteed.