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Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 616 of 982
REJ09B0023-0400
Some registers in channels 3 and 4 concerned are listed below: total 21 registers of TCR_3 and
TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and TIORL_4; TIER_3 and
TIER_4; TCNT_3 and TCNT_4; TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR;
TGCR; TCDR; and TDDR.
This function enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU
access to the mode registers, control register, and counters. In access disabled state, an undefined
value is read from the registers concerned, and cannot be modified.
Halting of PWM Output by External Signal: The 6-phase PWM output pins can be set
automatically to the high-impedance state by inputting specified external signals. There are four
external signal input pins.
See section 18.9, Port Output Enable (POE), for details.
18.5 Interrupts
18.5.1 Interrupts and Priority
There are three kinds of MTU interrupt source; TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priority can be changed by the interrupt controller, however the priority within a
channel is fixed.
Table 18.42 lists the MTU interrupt sources.