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Section 10 Interrupt Controller (INTC)
Rev. 4.00 Sep. 14, 2005 Page 219 of 982
REJ09B0023-0400
Section 10 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
10.1 Features
The INTC has the following features:
• 16 levels of interrupt priority can be set
By setting the ten interrupt-priority registers, the priorities of on-chip peripheral modules, and
IRQ interrupts can be selected from 16 levels for individual request sources.
• NMI noise canceler function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as a noise
canceler.
• IRQ interrupts can be set
Detection of low level, rising edge, falling edge, or high level
• Interrupts can be enabled or disabled
Interrupts can be enabled or disabled individually for each interrupt source with the interrupt
mask registers (IMR) and interrupt mask clear registers (IMCR).