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Section 6 Power-Down Modes
Rev. 4.00 Sep. 14, 2005 Page 169 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
6 0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
5 MSTP35 0 R/W Module Stop 35
When the MSTP35 bit is set to 1, supply of the clock
to the CMT0 stops.
0: The CMT0 runs.
1: Supply of the clock to the GMT0 stops.
4 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
3 MSTP33 0 R/W Module Stop 33
When the MSTP33 bit is set to 1, supply of the clock
to the ADC stops.
0: The ADC runs.
1: Supply of the clock to the ADC stops.
2 MSTP32 0 R/W Module Stop 32
When the MSTP32 bit is set to 1, supply of the clock
to the SCIF2 stops.
0: The SCIF2 runs.
1: Supply of the clock to the SCIF2 stops.
1 MSTP31 0 R/W Module Stop 31
When the MSTP31 bit is set to 1, supply of the clock
to the SCIF1 stops.
0: The SCIF1 runs.
1: Supply of the clock to the SCIF1 stops.
0 MSTP30 0 R/W Module Stop 30
When the MSTP30 bit is set to 1, supply of the clock
to the SCIF0 stops.
0: The SCIF0 runs.
1: Supply of the clock to the SCIF0 stops.