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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 413 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Descriptions
7
6
DL
DS
0
0
R/W
R/W
DREQ Level and DREQ Edge Select
These bits specify the sampling method of the DREQ
pin input and the sampling level.
These bits are valid only in CHCR_0 and CHCR_1.
These bits are always read as 0 in CHCR_2 and
CHCR_3. The write value should always be 0.
In channels 0 and 1, also, if the transfer request source
is specified as an on-chip peripheral module or if an
auto-request is specified, the specification by this bit is
ignored.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
5 TB 0 R/W Transfer Bus Mode
This bit specifies the bus mode when DMA transfers
data.
0: Cycle steal mode (Initial Value)
1: Burst mode
Set this bit to 0 when the on-chip peripheral module is
requesting DMA transfer, the setting for the transfer
count mode bit is 0, and the source of the transfer
request is the MTU.
4
3
TS1
TS0
0
0
R/W
R/W
Transmit Size
TS1 and TS0 specify the size of data to be transferred.
Select the size of data to be transferred when the
source or destination is an on-chip peripheral module
register of which transfer size is specified.
00: Byte size
01: Word size (two bytes)
10: Longword size (four bytes)
11: 16-byte unit (four longword transfers)