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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 318 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
6 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
5
4
3
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select
Select the clock input to count-up the refresh timer
counter (RTCNT).
000: Stop the counting-up
001: Bφ/4
010: Bφ/16
011: Bφ/64
100: Bφ/256
101: Bφ/1024
110: Bφ/2048
111: Bφ/4096
2
1
0
RRC2
RRC1
RRC0
0
0
0
R/W
R/W
R/W
Refresh Count
Specify the number of continuous refresh cycles, when
the refresh request occurs after the coincidence of the
values of the refresh timer counter (RTCNT) and the
refresh time constant register (RTCOR). These bits
can make the period of occurrence of refresh long.
000: Once
001: Twice
010: 4 times
011: 6 times
100: 8 times
101: Reserved (Setting prohibited)
110: Reserved (Setting prohibited)
111: Reserved (Setting prohibited)