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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 357 of 982
REJ09B0023-0400
Single Write: A write access ends in one cycle when data is written in non-cacheable region and
the data bus width is larger than or equal to access size.
Figure 12.22 shows the single write basic timing.
TapTr Tc1 Trwl
CKIO
A25 to A0
CSn
RD/WR
RASL, RASU
DQMxx
D31 to D0
BS
DACKn*
2
A12/A11*
1
CASL, CASU
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.22 Single Write Basic Timing (Auto-Precharge)