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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 304 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
17
16
BW1
BW0
0
0
R/W
R/W
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or later access cycles in burst
access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 13 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
12
11
SW1
SW0
0
0
R/W
R/W
Number of Delay Cycles from Address, CSn Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles