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Rev. 4.00 Sep. 14, 2005 Page xxxiii of l
Figure 13.8 Example of DMA Transfer Timing in Single Address Mode..................................436
Figure 13.9 DMA Transfer Example in the Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection).........................................................437
Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection).......................................................438
Figure 13.11 DMA Transfer Example in the Burst Mode
(Dual Address, DREQ Low Level Detection).......................................................438
Figure 13.12 Bus State when Multiple Channels Are Operating................................................440
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............441
Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 441
Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection .....................441
Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection ....................442
Figure 13.17 Example of DREQ Input Detection in Burst Mode Level Detection ....................442
Figure 13.18 BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword
Access to 16-Bit Device) ...................................................................................... 443
Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
When DACK is Divided to 4 by Idle Cycles ........................................................447
Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
When DACK is Divided to 2 by Idle Cycles ........................................................447
Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
When DACK is Divided to 4 by Idle Cycles ........................................................448
Figure 13.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
When DACK is Divided to 2 by Idle Cycles ........................................................449
Section 14 U Memory
Figure 14.1 U Memory Address Mapping..................................................................................452
Section 15 User Debugging Interface (H-UDI)
Figure 15.1 Block Diagram of H-UDI........................................................................................455
Figure 15.2 TAP Controller State Transitions ............................................................................468
Figure 15.3 H-UDI Data Transfer Timing..................................................................................470
Figure 15.4 H-UDI Reset............................................................................................................470
Section 16 I2C Bus Interface 2 (IIC2)
Figure 16.1 Block Diagram of I
2
C Bus Interface 2..................................................................... 474
Figure 16.2 External Circuit Connections of I/O Pins................................................................ 475
Figure 16.3 I
2
C Bus Formats ...................................................................................................... 488
Figure 16.4 I
2
C Bus Timing........................................................................................................ 488
Figure 16.5 Master Transmit Mode Operation Timing (1).........................................................490
Figure 16.6 Master Transmit Mode Operation Timing (2).........................................................490
Figure 16.7 Master Receive Mode Operation Timing (1)........................................................... 492
Figure 16.8 Master Receive Mode Operation Timing (2)........................................................... 493