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Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 76 of 982
REJ09B0023-0400
Shift Instructions
Table 2.22 Shift Instructions
Instruction
Instruction Code
Operation
Execution
States
T Bit
ROTL Rn 0100nnnn00000100 T ← Rn ← MSB 1 MSB
ROTR Rn 0100nnnn00000101 LSB → Rn → T 1 LSB
ROTCL Rn 0100nnnn00100100 T ← Rn ← T 1 MSB
ROTCR Rn 0100nnnn00100101 T → Rn → T 1 LSB
SHAD Rm,Rn 0100nnnnmmmm1100 Rm ≥ 0: Rn << Rm → Rn
Rm < 0: Rn >> Rm →
[MSB → Rn]
1 —
SHAL Rn 0100nnnn00100000 T ← Rn ← 0 1 MSB
SHAR Rn 0100nnnn00100001 MSB → Rn → T 1 LSB
SHLD Rm,Rn 0100nnnnmmmm1101 Rm ≥ 0: Rn << Rm → Rn
Rm < 0: Rn >> Rm →
[0 → Rn]
1 —
SHLL Rn 0100nnnn00000000 T ← Rn ← 0 1 MSB
SHLR Rn 0100nnnn00000001 0 → Rn → T 1 LSB
SHLL2 Rn 0100nnnn00001000 Rn << 2 → Rn 1 —
SHLR2 Rn 0100nnnn00001001 Rn >> 2 → Rn 1 —
SHLL8 Rn 0100nnnn00011000 Rn << 8 → Rn 1 —
SHLR8 Rn 0100nnnn00011001 Rn >> 8 → Rn 1 —
SHLL16 Rn 0100nnnn00101000 Rn << 16 → Rn 1 —
SHLR16 Rn 0100nnnn00101001 Rn >> 16 → Rn 1 —