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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 326 of 982
REJ09B0023-0400
CKIO
A25 to A0
RD/WR
D15 to D0
DACKn
CSn
T1 T2 T1 T2
RD
WEn
BS
WAIT
D15 to D0
Read
Write
*
Note:
*
The waveform for DACKn is when active low is specified.
Figure 12.5 Continuous Access for Normal Space 2
Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 1
(Access Wait = 0, Cycle Wait = 0)