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Section 21 A/D Converter
Rev. 4.00 Sep. 14, 2005 Page 801 of 982
REJ09B0023-0400
Table 21.2 Analog Input Channels and A/D Data Registers
Analog Input Channel A/D Data Register Module
AN0 ADDRA0
AN1 ADDRB0
AN2 ADDRC0
AN3 ADDRD0
A/D0
AN4 ADDRA1
AN5 ADDRB1
AN6 ADDRC1
AN7 ADDRD1
A/D1
21.2.2 A/D Control/Status Registers (ADCSR0, ADCSR1)
ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter,
and enable or disable starting of A/D conversion by external trigger input.
ADCSR is initialized to H'0040 by a power-on reset and in standby mode.
Bit Bit Name
Initial
Value R/W Description
15 ADF 0 R/(W)* A/D End Flag
Indicates the end of A/D conversion.
[Clearing conditions]
• Cleared by reading ADF while ADF = 1, then
writing 0 to ADF
• Cleared when DMAC is activated by ADI interrupt
and ADDR is read
[Setting conditions]
• Single mode: A/D conversion ends
• Multi mode: A/D conversion ends cycling through
the selected channels
• Scan mode: A/D conversion ends cycling through
the selected channels