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Section 20 USB Function Module
Rev. 4.00 Sep. 14, 2005 Page 795 of 982
REJ09B0023-0400
20.10.4 Assigning Interrupt Source for EP0
Interrupt sources (bits 0 to 3) for EP0 that are assigned to USBIFR0 of this module must be
assigned to the same interrupt pin using USBISR0.
20.10.5 Clearing FIFO when Setting DMA Transfer
Clearing the endpoint 1 data register (USBEPDR1) is impossible when DMA transfer is enabled
(USBDMAR/EP1DMAE = 1) for endpoint 1. To clear this register, cancel DMA transfer.
20.10.6 Manual Reset for DMA Transfer
Do not input a manual reset during DMA transfer for endpoints 1 and 2. Correct operation cannot
be guaranteed.
20.10.7 USB Clock
Input the USB clock (UCLK) before setting the register in this module.
20.10.8 Using TR Interrupt
Note that the following when using the transfer request interrupt (TR interrupt) for interrupt-IN
transfer of EP0i/EP2/EP3.
The TR interrupt flag is set when the IN token is sent from the USB host and there is no data in
the FIFO of the EP. However, TR interrupts occur continuously at the timing shown in figure
20.24. Make sure that no malfunction occurs in these cases.
Note: This module checks NAK acknowledgement if there is no data in the FIFO of the EP
when receiving the IN token. However the TR interrupt flag is set after transmitting the
NAK handshake. Therefore, when writing the USBTRG/PKTE bit is later than the next IN
token, the TR interrupt flag is set again.