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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 286 of 982
REJ09B0023-0400
12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
This register specifies various wait cycles for memory accesses. The bit configuration of this
register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the
CSn space bus control register (CSnBCR). Specify the CSnWCR register before accessing the
target area. Specify CSnBCR register first, then specify the CSnWCR register.
CSnWCR is initialized to H'00000500 by a power-on reset, and it is not initialized by a manual
reset and in the standby mode.
Normal Space, Byte-Selection SRAM, MPX-I/O:
• CS0WCR
Bit Bit Name
Initial
Value R/W Description
31 to 13 * All 0 R/W Reserved
When the normal space interface and SRAM interface
with byte selection are specified, these bits should be
set to 0.
12
11
SW1
SW0
0
0
R/W
R/W
Number of Delay Cycles from Address, CSn Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles