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Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 686 of 982
REJ09B0023-0400
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
receive-error interrupts are requested independently. The direct memory access controller
(DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receive-
FIFO-data-full interrupt.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• In asynchronous, on-chip modem control functions (RTS and CTS).
• The quantity of data in the transmit and receive FIFO registers and the number of receive
errors of the receive data in the receive FIFO register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 19.1 shows a block diagram of the SCIF for each channel.