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Section 16 I
2
C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 507 of 982
REJ09B0023-0400
16.6 Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 16.22 shows the timing of the bit synchronous circuit and table 16.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL
V
IH
SCL monitor
timing reference
clock
Internal SCL
Figure 16.22 The Timing of the Bit Synchronous Circuit
Table 16.4 Time for Monitoring SCL
CKS3 CKS2 CKS2CYC Time for Monitoring SCL
0 6.5 pcyc 0
1 5.5 pcyc
0 18.5 pcyc
0
1
1 17.5 pcyc
0 16.5 pcyc 0
1 15.5 pcyc
0 40.5 pcyc
1
1
1 39.5 pcyc
Note: The pcyc indicates the peripheral clock cycle.