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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 361 of 982
REJ09B0023-0400
Tc4
Tpw
Tp Tc2 Tc3
Tc1
Td4Td2 Td3
Td1
TdeTr
CKIO
A25 to A0
CSn
RD/WR
RASL, RASU
DQMxx
D31 to D0
BS
DACKn*
2
A12/A11*
1
CASL, CASU
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.25 Burst Read Timing
(Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1)