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Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 930 of 982
REJ09B0023-0400
Ta1
Ta2
Ta3
T1
Tw
Tw T 2
t
AD1
t
CSD1
t
AD1
t
RWD1
t
RWD1
t
CSD1
t
RSD
t
RSD
t
RDS1
t
WED1
t
WED1
Data
Data
t
BSD
t
BSD
t
WTH1
t
WTS1
t
AHD
t
AHD
t
WTH1
t
WTS1
t
DACD
t
DACD
Address
t
WDH1
t
WDD1
t
MAD
CKIO
A25 to A0
CS5B
RD/WR
RD
AH
D15 to D0
Read
WE1 to WE0
BS
WAIT
DACKn*
D15 to D0
Write
Address
t
MAH
t
MAD
t
AHD
Note: * Waveform for DACKn when active low is selected.
t
MAH
t
RDH1
Figure 25.18 MPX-IO Interface Bus Cycle
(Three Address Cycles, One Software Wait Cycle, One External Wait Cycle)