Filter
Top Products
Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 308 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
9 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
8
7
A3CL1
A3CL0
1
0
R/W
R/W
CAS Latency for Area 3
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6, 5 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
4
3
TRWL1*
TRWL0
0
0
R/W
R/W
Number of Auto-Precharge Startup Wait Cycles
Specify the number of minimum precharge startup wait
cycles during the periods shown below.
• From issuing of the WRITA command by this LSI to
starting of auto-precharge in SDRAM
The number of cycles from issuing the WRITA
command to issuing the ACTV command for the
same bank. See the SDRAM data sheets to
confirm the number of cycles precede issuing of
auto-precharge after the SDRAM has received the
WRITA command. Set these bits so that the
confirmed cycles should be equal to or less than
the cycles specified by these bits.
• From issuing of the WRIT command by this LSI to
issuing of the PRE command
When different row addresses are accessed from
the same bank address in bank-active mode
The setting for areas 2 and 3 is common.
00: No cycle (Initial value)
01: 1 cycle
10: 2 cycles
11: 3 cycles