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Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 589 of 982
REJ09B0023-0400
Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 18.30 shows an example
of procedure for selecting the reset synchronized PWM mode.
7
1
2
3
4
Stop counting
Select counter clock and
counter clear source
Set TGR
Reset-synchronized
PWM mode
Brushless DC motor
control setting
Set TCNT
5
Enable waveform output
Set reset-synchronized
PWM mode
6
PWM cycle output enabling,
PWM output level setting
8
Start count operation
9
Reset-synchronized PWM mode
Clear the CST3 and CST4 bits in the TSTR to 0 to halt the
counting of TCNT. The reset-synchronized PWM mode must be
set up while TCNT_3 and TCNT_4 are halted.
Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3
to select the counter clock and clock edge for channel 3. Set
bits CCLR2 to CCLR0 in the TCR_3 to select TGRA compare-
match as a counter clear source.
When performing brushless DC motor control, set bit BDC in the
timer gate control register (TGCR) and set the feedback signal
input source and output chopping or gate signal direct output.
Reset TCNT_3 and TCNT_4 to H'0000.
TGRA_3 is the period register. Set the waveform period value
in TGRA_3. Set the transition timing of the PWM output
waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times
within the compare-match range of TCNT_3.
X ≤ TGRA_3 (X: set value).
Select enabling/disabling of toggle output synchronized with the
PMW cycle using bit PSYE in the timer output control register
(TOCR), and set the PWM output level with bits OLSP and
OLSN.
Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the reset-
synchronized PWM mode. TIOC3A, TIOC3B, TIOC3D, TIOC4A,
TIOC4B, TIOC4C and TIOC4D function as PWM output pins.
Do not set to TMDR_4.
Set the enabling/disabling of the PWM waveform output pin in
TOER.
Set the CST3 bit in the TSTR to 1 to start the count operation.
1
2
3
4
5
7
6
8
9
The output waveform starts toggle operation at the point
of TCNT_3 = TGRA_3 = X by setting X = TGRA,
i.e., cycle = duty.
Notes: *
Figure 18.30 Procedure for Selecting the Reset-Synchronized PWM Mode