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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 319 of 982
REJ09B0023-0400
12.4.6 Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in
RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to
0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must
be H'A55A to cancel write protection. This counter is initialized to H'00000000 by a power-on
reset, and it is not initialized by a manual reset and in the standby mode.
Bit Bit Name
Initial
Value R/W Description
31 to 8 All 0 R Reserved
These bits are always read as 0.
7 to 0 All 0 R/W 8-Bit Counter
12.4.7 Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1
and RTCNT is cleared to 0.
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.
This request is maintained until the refresh operation is performed. If the request is not processed
when the next matching occurs, the previous request is ignored.
When the RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write
protection. This register is initialized to H'00000000 by a power-on reset, and it is not initialized
by a manual reset and in the standby mode.
Bit Bit Name
Initial
Value R/W Description
31 to 8 All 0 R Reserved
These bits are always read as 0.
7 to 0 All 0 R/W 8-Bit Counter