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Section 21 A/D Converter
Rev. 4.00 Sep. 14, 2005 Page 811 of 982
REJ09B0023-0400
Pφ
Write
signal
ADF
ADCSR
write cycle
Input sampling
timing
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
[Legend]
Address
ADCSR address
t
D
t
SPL
t
CONV
Figure 21.5 A/D Conversion Timing
Table 21.3 A/D Conversion Time (Single Mode)
CKS1 = 1, CKS0 = 1 CKS1 = 1, CKS0 = 1 CKS1 = 1, CKS0 = 1
Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
A/D conversion
start delay
t
D
18 — 21 10 — 13 6 — 9
Input sampling
time
t
SPL
— 129 — — 65 — — 33 —
A/D conversion
time
t
CONV
535 — 545 275 — 285 141 — 151
Note: Values in the table are numbers of states (t
cyc
).
Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode)
CKS1 CKS0 Conversion Time (t
cyc
)
0 128 (constant)
0
1 256 (constant)
0 512 (constant) 1
1 Reserved