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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 428 of 982
REJ09B0023-0400
On-Chip Peripheral Module Request: In this mode, the transfer is performed in response to the
DMA transfer request signal of an on-chip peripheral module. Signals that request DMA transfer
include A/D conversion-completed transfer requests from A/D converter 0, compare-match
transfer requests from the CMT0 timer, transmit-data empty transfer requests and receive-data full
transfer requests from the SCIF0 to SCIF2 that are set by DMARS0 and 1, compare-match and
input-capture interrupts from the MTU0 to MTU4 timers, transmit-data-empty transfer requests
and receive-data-full transfer requests from the USB module, A/D conversion-completed transfer
requests from A/D converter 1, and compare-match transfer requests from the CMT1 timer.
When the transfer request is a transmit-data-empty transfer request, set the transfer destination as
the corresponding SCIF transmit-data register. Likewise, when the transfer request is a receive-
data full transfer request, set the transfer destination as the corresponding SCIF receive-data
register. Requests from the USB are handled in an analogous way. If a transfer is requested from
the A/D converter 0 and A/D converter 1, the transfer source must be the A/D data register
(ADDR). Any address can be specified for data source and destination, when transfer request is
generated by CMT0, CMT1, and MTU0 to MTU4.
Table 13.7 Selecting On-Chip Peripheral Module Request Modes with the RS3 to RS0 Bits
CHCR DMARS
RS[3:0] MID RID
DMA Transfer
Request
Source
DMA Transfer
Request Signal
Source Destination Bus Mode
1110 Any Any A/D converter 0 ADI (A/D conversion
end interrupt)
ADDR Any Cycle steal
1111 Any Any CMT0 Compare-match transfer
request
Any Any Burst/
cycle steal
1000 100010 00 SCIF0
transmitter
TXI (transmit data FIFO
empty interrupt)
Any SCFTDR0 Cycle steal
01 SCIF0 receiver RXI (receive data FIFO
full interrupt)
SCFRDR0 Any Cycle steal
100100 00 SCIF1
transmitter
TXI (transmit data FIFO
empty interrupt)
Any SCFTDR1 Cycle steal
01 SCIF1 receiver RXI (receive data FIFO
full interrupt)
SCFRDR1 Any Cycle steal
010000 00 SCIF2
transmitter
TXI (transmit data FIFO
empty interrupt)
Any SCFTDR2 Cycle steal
01 SCIF2 receiver RXI (receive data FIFO
full interrupt)
SCFRDR2 Any Cycle steal