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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 362 of 982
REJ09B0023-0400
Tr Tc1
CKIO
A25 to A0
CSn
RD/WR
RASL, RASU
DQMxx
D31 to D0
BS
DACKn*
2
A12/A11*
1
CASL, CASU
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.26 Single Write Timing (Bank Active, Different Bank)