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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 346 of 982
REJ09B0023-0400
Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
(4)-2
Setting
BSZ
1, 0
A2/3
ROW
1, 0
A2/3
COL
1, 0
11 (32 bits) 00 (11 bits) 00 (8 bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
SDRAM Pin Function
A17 A25 A17
A16 A24 A16
A15 A23 A15
Unused
A14 A22*
2
A22*
2
A13 (BA1)
A13 A21*
2
A21*
2
A12 (BA0)
A12 A20 A20 A11
Specifies bank
Address
A11 A19 L/H*
1
A10/AP Specifies
address/precharge
A10 A18 A10 A9
A9 A17 A9 A8
A8 A16 A8 A7
A7 A15 A7 A6
A6 A14 A6 A5
A5 A13 A5 A4
A4 A12 A4 A3
A3 A11 A3 A2
A2 A10 A2 A1
A1 A9 A1 A0
Address
A0 A8 A0 Unused
Example of connected memory
64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification