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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 371 of 982
REJ09B0023-0400
Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed
after powering on. To perform synchronous DRAM initialization correctly, the bus state controller
registers must first be set, followed by a write to the synchronous DRAM mode register. In
synchronous DRAM mode register setting, the address signal value at that time is latched by a
combination of the CSn, RASU, RASL, CASU, CASL, and RD/WR signals. If the value to be set
is X, the bus state controller provides for value X to be written to the synchronous DRAM mode
register by performing a write to address H'A4FD4000 + X for area 2 synchronous DRAM, and to
address H'A4FD5000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but
the mode write is performed as a byte-size access. To set burst read/single write, CAS latency 2 to
3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a
byte-size access to the addresses shown in table 12.15. In this time 0 is output at the external
address pins of A12 or later.
Table 12.15 Access Address in SDRAM Mode Register Write
• Setting for Area 2
Burst read/single write (burst length 1):
Data Bus Width CAS Latency Access Address External Address Pin
16 bits 2 H'A4FD4440 H'0000440
3 H'A4FD4460 H'0000460
32 bits 2 H'A4FD4880 H'0000880
3 H'A4FD48C0 H'00008C0
Burst read/burst write (burst length 1):
Data Bus Width CAS Latency Access Address External Address Pin
16 bits 2 H'A4FD4040 H'0000040
3 H'A4FD4060 H'0000060
32 bits 2 H'A4FD4080 H'0000080
3 H'A4FD40C0 H'00000C0