Filter
Top Products
Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 334 of 982
REJ09B0023-0400
T1
CKIO
A25 to A16
CS5B
RD/WR
RD
D7 to D0 or
D15 to D0
WEn
D7 to D0 or
D15 to D0
BS
Read
Write
T2
DACKn*
Ta1 Ta2 Ta3
AH
Address
Address Data
Data
Tadw Tw Twx
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 12.14 Access Timing for MPX Space
(Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)