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Section 16 I
2
C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 482 of 982
REJ09B0023-0400
16.3.4 I
2
C Bus Interrupt Enable Register (ICIER)
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits
received. ICIER is initialized to H'00 by a power-on reset.
Bit Bit Name
Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables
or disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is
disabled.
1: Transmit data empty interrupt request (TXI) is
enabled.
6 TEIE 0 R/W Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(TEI) at the rising of the ninth clock while the TDRE bit
in ICSR is 1. TEI can be canceled by clearing the TEND
bit or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
5 RIE 0 R/W Receive Interrupt Enable
This bit enables or disables the receive data full
interrupt request (RXI) when a receive data is
transferred from ICDRS to ICDRR and the RDRF bit in
ICSR is set to 1. RXI can be canceled by clearing the
RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) are disabled.
1: Receive data full interrupt request (RXI) are enabled.
4 NAKIE 0 R/W NACK Receive Interrupt Enable
This bit enables or disables the NACK detection
interrupt request (NAKI) when the NACKF or AL/OVE
bit in ICSR is set. NAKI can be canceled by clearing the
NACKF, AL/OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.