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Rev. 4.00 Sep. 14, 2005 Page xxxii of l
Figure 12.28 Single Write Timing
(Bank Active, Different Row Addresses in the Same Bank) ................................ 364
Figure 12.29 Auto-Refresh Timing ............................................................................................ 366
Figure 12.30 Self-Refresh Timing..............................................................................................367
Figure 12.31 Low-Frequency Mode Access Timing .................................................................. 369
Figure 12.32 Power-Down Mode Access Timing ...................................................................... 370
Figure 12.33 Synchronous DRAM Mode Write Timing (Based on JEDEC)............................. 373
Figure 12.34 EMRS Command Issue Timing.............................................................................374
Figure 12.35 Deep Power-Down Mode Transition Timing........................................................ 375
Figure 12.36 Burst ROM Access Timing (Clock Asynchronous)
(Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted
in First Access = 2, Wait Cycles Inserted in Second and
Subsequent Accesses = 1)..................................................................................... 377
Figure 12.37 Byte-Selection RAM Basic Access Timing (BAS = 0)......................................... 378
Figure 12.38 Byte-Selection RAM Basic Access Timing (BAS = 1)......................................... 379
Figure 12.39 Byte-Selection SRAM Wait Timing (BAS = 1) (SW[1:0] = 01,
WR[3:0] = 0001, HW[1:0] = 01) .......................................................................... 380
Figure 12.40 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM ............. 381
Figure 12.41 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............. 381
Figure 12.42 Burst MPX Device Connection Example.............................................................. 382
Figure 12.43 Burst MPX Space Access Timing (Single Read, No Wait, or Software Wait 1) .. 383
Figure 12.44 Burst MPX Space Access Timing
(Single Write, Software Wait 1, Hardware Wait 1) .............................................. 384
Figure 12.45 Burst MPX Space Access Timing (Burst Read, No Wait, or Software Wait 1,
CS6BWCR.MPXMD = 0) ....................................................................................385
Figure 12.46 Burst MPX Space Access Timing (Burst Write, No Wait,
CS6BWCR.MPXMD = 0) ....................................................................................386
Figure 12.47 Burst ROM Access Timing (Clock Synchronous)
(Burst Length = 8, Wait Cycles Inserted in First Access = 2,
Wait Cycles Inserted in Second and Subsequent Accesses = 1) ...........................387
Figure 12.48 Bus Arbitration Timing (Clock Mode 7 or CMNCR.HIZCNT = 1) ..................... 400
Section 13 Direct Memory Access Controller (DMAC)
Figure 13.1 Block Diagram of the DMAC .................................................................................406
Figure 13.2 DMA Transfer Flowchart........................................................................................ 425
Figure 13.3 Round-Robin Mode.................................................................................................430
Figure 13.4 Changes in Channel Priority in Round-Robin Mode............................................... 431
Figure 13.5 Data Flow of Dual Address Mode...........................................................................433
Figure 13.6 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory) ................................ 434
Figure 13.7 Data Flow in Single Address Mode......................................................................... 435