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Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 635 of 982
REJ09B0023-0400
T1 T2
H'FFFE H'FFFF N N + 1
H'FFFF
M
M
N
P
QP
M
Disabled
TCNT_2 write data
TCNT_2 address
TCNT write cycle
Pφ
Address
Write signal
TCNT_2
TGR2A_2 to
TGR2B_2
Ch2 compare-
match signal A/B
TCNT_1 input
clock
TCNT_1
TGRA_1
Ch1 compare-
match signal A
TGRB_1
Ch1 input capture
signal B
TCNT_0
TGRA_0 to
TGRD_0
Ch0 input capture
signal A to D
Figure 18.79 TCNT_2 Write and Overflow/Underflow Conflict with Cascade Connection