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Section 4 Clock Pulse Generator (CPG)
Rev. 4.00 Sep. 14, 2005 Page 152 of 982
REJ09B0023-0400
4.6 Notes on Board Design
Note on Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and
CL2, and feedback resistor R1 as close to the XTAL and EXTAL pins as possible. In addition, to
minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be
attached to the resonator must be grounded to the same ground. Do not bring wiring patterns close
to these components.
Signal lines prohibited
CL1
CL2
EXTAL
XTAL
This LSI
Rl
The values for CL1, CL2, and
the damping resistance RI
should be determined after
consultation with the crystal
resonator manufacturer.
Note:
Reference value
CL1 = 10 to 33 pF
CL2 = 10 to 33 pF
Rl = 1MΩ
Figure 4.2 Note on Using a Crystal Resonator
Notes on Using External Clocks: When external clocks are input from the EXTAL pin, leave the
XTAL pin open. In order to prevent a malfunction due to the reflection noise caused in a signal
line which connected to XTAL pin, cut this signal line as short as possible.
Notes on Bypass Capacitor: A multilayer ceramic capacitor must be inserted for each pair of Vss
and Vcc as a bypass capacitor. The bypass capacitor must be inserted as close as possible to the
power supply pins of the LSI. Note that the capacitance and frequency characteristics of the
bypass capacitor must be appropriate for the operating frequency of the LSI.
• A pair of Vss and VCC for the input/output power supply
C1 to D1, M4 to M3, V1 to W1, U7 to V7, U12 to V12, Y18 to Y19, M19 to M18, H17 to
H18, C20 to B20, A18 to A17, D14 to C14, D13 to C13, D8 to C8, A3 to A2
• A pair of Vss and Vcc for the digital modules
F3 to F4, K3 to K4, U4 to T4, V6 to U6, V10 to U10, U17 to U16, R18 to R17, L18 to L17,
D17 to E17, C15 to D15, C11 to D11, D4 to D5
• A pair of Vss and Vcc for the on-chip oscillator
K20 to K17, K18 to J20