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Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 429 of 982
REJ09B0023-0400
CHCR DMARS
RS[3:0] MID RID
DMA
Transfer
Request
Source
DMA Transfer
Request Signal Source
Desti-
nation Bus Mode
1000 101010 00 MTU0 TGI0A
(input capture interrupt/
compare match interrupt)
Any Any Burst/
cycle steal
110000 00 MTU1 TGI1A
(input capture interrupt/
compare match interrupt)
Any Any Burst/
cycle steal
110010 00 MTU2 TGI2A
(input capture interrupt/
compare match interrupt)
Any Any Burst/
cycle steal
110100 00 MTU3 TGI3A
(input capture interrupt/
compare match interrupt)
Any Any Burst/
cycle steal
111010 00 MTU4 TGI4A
(input capture interrupt/
compare match interrupt)
Any Any Burst/
cycle steal
101000 00 USB transmitter EP2FIFO empty transfer
request
Any USBEPDR2 Cycle steal
01 USB
receiver
EP1FIFO full transfer
request
USBEPDR1 Any Cycle steal
101100 00 A/D converter 1 ADI (A/D conversion
end interrupt)
ADDR1 Any Cycle steal
111100 00 CMT1 Compare-match transfer
request
Any Any Burst/
cycle steal
13.4.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. The four modes (fixed mode 1, fixed mode 2,
channel selective round-robin mode, and all-channel round-robin mode) are selected using the
priority bits PR0, PR1, and RC0 to RC3 in the DMA operation register (DMAOR).
Fixed Mode: In these modes, the priority levels among the channels remain fixed. There are two
kinds of fixed modes as follows:
Fixed mode 1: CH0 > CH1 > CH2 > CH3
Fixed mode 2: CH0 > CH2 > CH3 > CH1