Filter
Top Products
Section 7 Cache
Rev. 4.00 Sep. 14, 2005 Page 183 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
0 CE 0 R/W Cache Enable
Indicates whether the cache function is used.
0: Cache not used
1: Cache used
7.2.2 Cache Control Register 2 (CCR2)
CCR2 is used to enable or disable the cache locking function and is valid in cache locking mode
only. In cache locking mode, the DSP bit (bit 12) in the status register (SR) of the CPU is set to 1.
Alternatively, the lock enable bit (bit 16) in CCR2 is set to 1. In the non-cache-locking mode, the
cache locking function is invalid.
When a cache miss occurs in cache locking mode by executing the prefetch instruction (PREF
@Rn), the line of data pointed to by Rn is loaded into the cache according to bits 9 and 8 (the
W3LOAD and W3LOCK bits) and bits 1 and 0 (the W2LOAD and W2LOCK bits) in CCR2. The
relationship between the setting of each bit and a way, to be replaced when the prefetch instruction
is executed, are listed in table 7.4. On the other hand, when the prefetch instruction is executed
and a cache hit occurs, new data is not fetched and the entry which is already enabled is held. For
example, when the prefetch instruction is executed with W3LOAD = 1 and W3LOCK = 1
specified in cache locking mode while one-line data already exists in way 0 which is specified by
Rn, a cache hit occurs and data is not fetched to way 3.
In the cache access other than the prefetch instruction in cache locking mode, ways to be replaced
by bits W3LOCK and W2LOCK are restricted. The relationship between the setting of each bit in
CCR2 and ways to be replaced are listed in table 7.5.
The program that change the contents of CCR2 should be placed in an address space that is not
cached.
CCR2 is initialized to H'00000000 by a power-on or manual reset and retain the previous value by
standby mode, module standby mode, and sleep mode.