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Section 4 Clock Pulse Generator (CPG)
Rev. 4.00 Sep. 14, 2005 Page 143 of 982
REJ09B0023-0400
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock
(Pφ), and a bus clock (Bφ). The CPG consists of an oscillator, PLL circuit, and divider circuit.
4.1 Features
The CPG has the following features.
• Three clock modes
The mode is selected from among the three clock modes by the selection of the following three
conditions: the frequency-divisor in use, whether the PLL is on or off, and whether the internal
crystal resonator or the input on the external clock-signal line is used.
• Three clocks generated independently
An internal clock (Iφ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip
peripheral modules; a bus clock (Bφ = CKIO) for the external bus interface.
• Frequency change function
Internal and peripheral clock frequencies can be changed independently using the PLL (phase
locked loop) circuit and divider circuit within the CPG. Frequencies are changed by software
using frequency control register (FRQCR) settings.
• Power-down mode control
The clock can be stopped for sleep mode, and standby mode and specific modules can be
stopped using the module standby function. For details on clock control in the low-power
consumption modes, see section 6, Power-Down Modes.
A block diagram of the CPG is given in figure 4.1.