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Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 716 of 982
REJ09B0023-0400
Bit Bit Name
Initial
value R/W Description
2 TFRST 0 R/W Transmit FIFO Data Register Reset
Disables the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
1 RFRST 0 R/W Receive FIFO Data Register Reset
Disables the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
0 LOOP 0 R/W Loop-Back Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD) and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled