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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 279 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
11 BLOCK 0 R/W Bus Clock
Specifies whether or not the BREQ signal is received.
0: Receives BREQ.
1: Does not receive BREQ.
10
9
DPRTY1
DPRTY0
0
0
R/W
R/W
DMA Burst Transfer Priority
Specify the priority for a refresh request/bus
mastership request during DMA burst transfer.
00: Accepts a refresh request and bus mastership
request during DMA burst transfer.
01: Accepts a refresh request but does not accept a
bus mastership request during DMA burst transfer.
10: Accepts neither a refresh request nor a bus
mastership request during DMA burst transfer.
11: Reserved (setting prohibited)
8
7
6
DMAIW2
DMAIW1
DMAIW0
0
0
0
R/W
R/W
R/W
Wait states between access cycles when DMA single
address transfer is performed.
Specify the number of idle cycles to be inserted after
an access to an external device with DACK when DMA
single address transfer is performed. The method of
inserting idle cycles depends on the contents of
DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycled inserted
100: 6 idle cycled inserted
101: 8 idle cycle inserted
110: 10 idle cycles inserted
111: 12 idle cycled inserted