Filter
Top Products
Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 438 of 982
REJ09B0023-0400
DREQ
CPU CPUBus cycle CPU DMAC DMAC CPU CPU DMAC DMAC CPU
Read/Write Read/Write
More than 16 or 64Bφ
(change by the CPU's condition of using bus)
Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)
2. Burst Mode
Once the bus mastership is obtained, the transfer is performed continuously until the transfer
end condition is satisfied. In the external request mode with low level detection of the DREQ
pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after
the DMAC transfer request that has already been accepted ends, even if the transfer end
conditions have not been satisfied.
The burst mode cannot be used for other than CMT0, CMT1, and MTU0 to MTU4 when the
on-chip peripheral module is the transfer request source. Figure 13.11 shows DMA transfer
timing in the burst mode.
CPU CPU CPU DMAC DMAC DMAC DMACDMAC DMAC CPU
DREQ
Bus cycle
Read Read ReadWrite Write
Write
Figure 13.11 DMA Transfer Example in the Burst Mode
(Dual Address, DREQ Low Level Detection)
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table
13.9 shows the relationship between request modes and bus modes by DMA transfer category.