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Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 626 of 982
REJ09B0023-0400
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DMA is activated, the flag is cleared automatically. Figure 18.68 shows the
timing for status flag clearing by the CPU, and figure 18.69 shows the timing for status flag
clearing by the DMA.
Status flag
Write signal
Address
TSR address
Interrupt
request signal
TSR write cycle
T1 T2
Pφ
Figure 18.68 Timing for Status Flag Clearing by the CPU
DMA transfer
request signal
Status falg
DMA falg clear
signal
Pφ
Figure 18.69 Timing for Status Flag Clearing by DMA Activation