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Section 6 Power-Down Modes
Rev. 4.00 Sep. 14, 2005 Page 170 of 982
REJ09B0023-0400
6.2.4 Standby Control Register 4 (STBCR4)
STBCR4 is a readable/writable 8-bit register used to select whether or not individual modules
operate in power-down mode. STBCR4 is initialized (to H'00) by a power-on reset, but retains its
previous value after a manual reset or a period in the standby mode. Only byte access is valid.
Bit Bit Name
Initial
Value R/W Description
7 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
6 MSTP46 0 R/W Module Stop 46
0: The USB module stops.
1: Supply of the clock to the USB is started.
5 MSTP45 0 R/W Module Stop 45
When the MSTP45 bit is set to 1, supply of the clock
to the MTU stops.
0: The MTU runs.
1: Supply of the clock to the MTU stops.
4 MSTP44 0 R/W Module Stop 44
When the MSTP44 bit is set to 1, supply of the clock
to the POE stops.
0: The POE runs.
1: Supply of the clock to the POE stops.
3 MSTP43 0 R/W Module Stop 43
When the MSTP43 bit is set to 1, supply of the clock
to the CMT1 stops.
0: The CMT1 runs.
1: Supply of the clock to the CMT1 stops.
2 MSTP42 0 R/W Module Stop 42
When the MSTP42 bit is set to 1, supply of the clock
to the IIC2 stops.
0: The IIC2 runs.
1: Supply of the clock to the IIC2 stops.
1, 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.