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Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 929 of 982
REJ09B0023-0400
t
AD1
t
AD1
T1
t
RWD1
t
RSD
t
WED1
t
WED1
t
WED1
t
RDS1
t
RDS1
t
RDH1
t
RDH1
t
AS
t
RSD
t
RSD
t
AH
t
RSD
t
AH
t
WED1
t
AH
t
AH
t
CSD1
t
WDD1
t
WDH1
t
WDH1
t
WDD1
t
BSD
t
BSD
t
DACD
t
DACD
t
DACD
t
DACD
t
BSD
t
BSD
t
RWD1
t
RWD1
t
RWD1
t
CSD1
t
CSD1
t
CSD1
tAS
t
AD1
t
AD1
Tw T2 Taw T1 Tw T2 Taw
t
WTH1
t
WTS1
t
WTH1
t
WTS1
WAIT
Note: * Waveform for DACKn when active low is selected.
CKIO
A25 to A0
CSn
RD/WR
RD
D15 to D0
Read
WEn
BS
DACKn*
D15 to D0
Write
Figure 25.17 Basic Bus Timing for Normal Space
(One Cycle of Software Wait, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle)