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Section 6 Power-Down Modes
Rev. 4.00 Sep. 14, 2005 Page 171 of 982
REJ09B0023-0400
6.3 Operation
6.3.1 Sleep Mode
1. Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from
the program execution state to sleep mode. Although the CPU halts immediately after
executing the SLEEP instruction, the contents of its internal registers remain unchanged. The
on-chip modules continue to run in sleep mode, but the on-chip memory is not accessible. If
the on-chip memory is accessed by, for example, the DMAC, the access is ignored and the
value read is not defined. Clock pulses continue to be output on the CKIO and CKIO2 pins. In
sleep mode, a high signal and low signal are output from the STATUS1 and STATUS0 pins,
respectively.
2. Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module) or reset.
Interrupts are accepted in sleep mode even when the BL bit in the SR register is 1. If
necessary, save SPC and SSR to the stack before executing the SLEEP instruction.
• Canceling with an Interrupt
When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and
interrupt exception handling is executed. A code indicating the interrupt source is set in the
INTEVT2 registers.
• Canceling with a Reset
Sleep mode is canceled by a power-on reset or a manual reset.