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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 349 of 982
REJ09B0023-0400
Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
(6)-1
Setting
BSZ
1, 0
A2/3
ROW
1, 0
A2/3
COL
1, 0
11 (32 bits) 00 (11 bits) 00 (8 bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
SDRAM Pin Function
A17 A26 A17
A16 A25 A16
Unused
A15 A24*
2
A24*
2
A14 (BA1)
A14 A23*
2
A23*
2
A13 (BA0)
Specifies bank
A13 A22 A13 A12
A12 A21 A12 A11
Address
A11 A20*
2
L/H*
1
A10/AP Specifies
address/precharge
A10 A19 A10 A9
A9 A18 A9 A8
A8 A17 A8 A7
A7 A16 A7 A6
A6 A15 A6 A5
A5 A14 A5 A4
A4 A13 A4 A3
A3 A12 A3 A2
A2 A11 A2 A1
A1 A10 A1 A0
Address
A0 A9 A0 Unused
Example of connected memory
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 9 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU
is not asserted.