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Rev. 4.00 Sep. 14, 2005 Page 981 of 982
REJ09B0023-0400
USBEPDR0i ....................................... 756
USBEPDR0o ...................................... 756
USBEPDR0s....................................... 757
USBEPSTL......................................... 763
USBEPSZ0o ....................................... 758
USBEPSZ1......................................... 759
USBFCLR .......................................... 761
USBIER.............................................. 754
USBIFR .............................................. 750
USBISR .............................................. 753
USBTRG ............................................ 759
USBXVERCR .................................... 764
WTCNT.............................................. 156
WTCSR .............................................. 157
Register Addresses ................................. 866
Register Bits ........................................... 876
Repeat end register ................................... 25
Repeat start register .................................. 25
Reset-synchronized PWM mode ............ 588
Rounding operation ................................ 115
Round-robin mode.................................. 430
S
Saved program counter............................. 25
Saved status register ................................. 25
Scan mode .............................................. 808
SDRAM interface................................... 335
Self-refreshing ........................................ 366
Serial communication interface with FIFO
................................................................ 685
Shadow area............................................ 274
Shift instructions....................................... 76
Shift operations....................................... 109
Single address mode ............................... 434
Single data addressing .............................. 53
Single mode............................................ 805
Slave address .......................................... 489
Sleep mode ..................................... 163, 171
Software standby mode........................... 163
Stall operations .......................................780
Standby control circuit............................ 145
Standby mode ......................................... 172
Start condition......................................... 489
Status register............................................25
Stop condition .........................................489
Synchronous DRAM Timing.................. 935
Synchronous operation.................... 568, 733
System control instructions.......................78
System registers ........................................35
T
T Bit ..........................................................45
TAP controller ........................................468
U
U memory ...............................................451
Unconditional trap ..................................208
USB bus power control method.............. 789
USB function module .............................747
User break controller...............................241
User break point trap...............................208
User debugging interface ........................455
V
Vector base register...................................25
W
Wait between access cycles .................... 387
Watchdog timer....................................... 155
Watchdog timer mode.............................160