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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 372 of 982
REJ09B0023-0400
• Setting for Area 3
Burst read/single write (burst length 1):
Data Bus Width CAS Latency Access Address External Address Pin
16 bits 2 H'A4FD5440 H'0000440
3 H'A4FD5460 H'0000460
32 bits 2 H'A4FD5880 H'0000880
3 H'A4FD58C0 H'00008C0
Burst read/burst write (burst length 1):
Data Bus Width CAS Latency Access Address External Address Pin
16 bits 2 H'A4FD5040 H'0000040
3 H'A4FD5060 H'0000060
32 bits 2 H'A4FD5080 H'0000080
3 H'A4FD50C0 H'00000C0
Mode register setting timing is shown in figure 12.33. A PALL command (all bank pre-charge
command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An
MRS command (mode register write command) is finally issued. Idle cycles, of which number is
specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the
first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR,
are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which
number is one or more, are inserted between the MRS and a command to be issued next.
It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after
power-on. Refer the manual of the SDRAM for the idle time to be needed. When the pulse width
of the reset signal is longer then the idle time, mode register setting can be started immediately
after the reset, but care should be taken when the pulse width of the reset signal is shorter than the
idle time.