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Section 14 U Memory
Rev. 4.00 Sep. 14, 2005 Page 451 of 982
REJ09B0023-0400
Section 14 U Memory
This LSI has on-chip U memory. It can be used by the CPU, DSP, and DMAC to store instructions
or data.
14.1 Features
The U memory features are listed in table 14.1.
Table 14.1 U Memory Specifications
Parameter Features
Addressing method Mapping is possible in space P0 or P2
Ports 2 independent read/write ports
• 8-/16-/32-bit access from the CPU (via L bus or I bus)
• 16-/32-bit access from the DSP (via L bus or I bus)
• 8-/16-32-bit access from the CPU (via I bus)
Size 128 kbytes
The U memory resides in addresses H'055F0000 to H'0560FFFF in space P0 or addresses
H'A55F0000 to H'A560FFFF (128 kbytes) in space P2. The U memory is divided into page 0 and
page 1 according to the addresses. The U memory can be accessed from the L bus and I bus.
In the event of simultaneous accesses to the same address from different buses, the priority order
is : I bus > L bus. Since this kind of conflict tends to lower U memory accessibility, it is advisable
to provide software measures to prevent such conflict as far as possible. For example, conflict will
not arise if different memory or different pages are accessed by each bus.
U memory is accessed by the CPU or DSP from space P0 via the I bus, a conflict with the DMAC
may occur on the I bus. Since this kind of conflict also tends to lower U memory accessibility, it is
advisable to provide software measures to prevent such conflict as far as possible. For example,
conflict on the I bus can be prevented by using space P2 when the U memory is accessed by the
CPU or DSP.