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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 394 of 982
REJ09B0023-0400
BSC Register Setting CPU Access DMAC Access
CSnBCR
Idle
Setting
CS3WCR.
WTRP
Setting
CS3WCR.
TRWL
Setting
Read to
Read
Write to
Write
Read to
Write
Write to
Read
Read to
Write
Write to
Read
1 2 3 3/3/3/3 5/5/5/5 3/3/4/5 5/5/5/5 3 5
1 3 0 4/4/4/4 3/3/3/3 4/4/4/5 3/3/3/3 4 3
1 3 1 4/4/4/4 4/4/4/4 4/4/4/5 4/4/4/4 4 4
1 3 2 4/4/4/4 5/5/5/5 4/4/4/5 5/5/5/5 4 5
1 3 3 4/4/4/4 6/6/6/6 4/4/4/5 6/6/6/6 4 6
2 0 0 3/3/3/3 2/2/2/3 3/3/4/5 2/2/2/2 3 2
2 0 1 3/3/3/3 2/2/2/3 3/3/4/5 2/2/2/2 3 2
2 0 2 3/3/3/3 2/2/2/3 3/3/4/5 2/2/2/2 3 2
2 0 3 3/3/3/3 3/3/3/3 3/3/4/5 3/3/3/3 3 3
2 1 0 3/3/3/3 2/2/2/2 3/3/4/5 2/2/2/2 3 2
2 1 1 3/3/3/3 2/2/2/2 3/3/4/5 2/2/2/2 3 2
2 1 2 3/3/3/3 3/3/3/3 3/3/4/5 3/3/3/3 3 3
2 1 3 3/3/3/3 4/4/4/4 3/3/4/5 4/4/4/4 3 4
2 2 0 3/3/3/3 2/2/2/3 3/3/4/5 2/2/2/2 3 2
2 2 1 3/3/3/3 3/3/3/3 3/3/4/5 3/3/3/3 3 3
2 2 2 3/3/3/3 4/4/4/4 3/3/4/5 4/4/4/4 3 4
2 2 3 3/3/3/3 5/5/5/5 3/3/4/5 5/5/5/5 3 5
2 3 0 4/4/4/4 3/3/3/3 4/4/4/5 3/3/3/3 4 3
2 3 1 4/4/4/4 4/4/4/4 4/4/4/5 4/4/4/4 4 4
2 3 2 4/4/4/4 5/5/5/5 4/4/4/5 5/5/5/5 4 5
2 3 3 4/4/4/4 6/6/6/6 4/4/4/5 6/6/6/6 4 6
4 0 0 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 0 1 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 0 2 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 0 3 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 1 0 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 1 1 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 1 2 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4
4 1 3 5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5 4