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Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 932 of 982
REJ09B0023-0400
25.3.5 Bus Cycle of Byte-Selection SRAM
Th
t
AD1
t
RSD
t
RSD
t
RDS1
t
CSD1
t
RWD1
T1 Twx T2 Tf
t
WDD1
t
BSD
t
WDH1
t
RDH1
t
AD1
t
CSD1
CKIO
A25 to A0
CSn
WEn
RD
D31 to D0
D31 to D0
Read
RD/WR
RD/WR
BS
WAIT
Write
t
DACD
t
DACD
t
BSD
t
WTS1
t
WTS1
t
RWD1
t
RWD1
t
RWD1
t
WED1
t
WED1
t
WTH1
t
WTH1
DACKn,
TENDn*
Note: * Waveform for DACKn and TENDn when active low is selected.
Figure 25.20 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One
Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))