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Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 675 of 982
REJ09B0023-0400
18.9.2 Pin Configuration
Table 18.44 Pin Configuration
Name Abbreviation I/O Description
Port output enable input pins POE0 to POE3 Input Input request signals to make high-
current pins high-impedance state
Table 18.45 shows output-level comparisons with pin combinations.
Table 18.45 Pin Combinations
Pin Combination I/O Description
TIOC3B/PTE[6] and TIOC3D/PTE[4] Output All high-current pins are made high-impedance
state when the pins simultaneously output low-level
for longer than 1 cycle.
TIOC4A/PTE[3] and TIOC4C/PTE[1] Output All high-current pins are made high-impedance
state when the pins simultaneously output low-level
for longer than 1 cycle.
TIOC4B/PTE[2] and TIOC4D/PTE[0] Output All high-current pins are made high-impedance
state when the pins simultaneously output low-level
for longer than 1 cycle.
18.9.3 Register Configuration
The POE has the two registers. The input level control/status register 1 (ICSR1) controls both
POE0 to POE3 pin input signal detection and interrupts. The output level control/status register
(OCSR) controls both the enable/disable of output comparison and interrupts.
Input Level Control/Status Register 1 (ICSR1): ICSR1 is a 16-bit readable/writable register
that selects the POE0 to POE3 pin input modes, controls the enable/disable of interrupts, and
indicates status.