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Section 20 USB Function Module
Rev. 4.00 Sep. 14, 2005 Page 784 of 982
REJ09B0023-0400
20.7 DMA Transfer
This module allows DMAC transfer for endpoints 1 and 2, excluding transfer of word and
longword.
If endpoint 1 contains at least one byte of valid receive data, a DMA transfer request is issued to
endpoint 1. If there is no valid data in endpoint 2, a DMA transfer request is issued to endpoint 2.
When EP1 DMAE in the USBDMA setting register is set to 1 to allow DMA transfer, 0-length
data received for endpoint 1 is ignored. When DMA transfer is set, it is unnecessary to write 1 to
the EP1 USBTRG/RDFN and EP2 USBTRG/PKTE bits. (1 must be written to the
USBTRG/PKTE bit for data that consists of the maximum number of bytes or less.) For EP1, the
FIFO buffer automatically becomes empty when all the received data is read. For EP2, the FIFO
automatically becomes full when the maximum number of bytes (64 bytes) is written to the FIFO
and then the data in the FIFO is transmitted. (See figures 20.15 and 20.16.)
20.7.1 DMA Transfer for Endpoint 1
If the received data for EP1 is transferred by DMA when the data on the currently selected FIFO
becomes empty, an equivalent processing of writing 1 to the USBTRG/RDFN bit is automatically
performed in the module. Therefore, do not write 1 to the EP1RDFN bit in USBTRG after reading
the data on one side of the FIFO. Correct operation cannot be guaranteed.
For example, if 150 bytes of data are received from the host, the equivalent processing of writing 1
to the USBTRG/RDFN bit is automatically performed internally in the three places in figure
20.15. This processing is done when the data on the currently selected FIFO becomes empty
meaning that the processing is to be automatically performed even if 64 bytes of data or less than
that are transferred.
RDFN
(automatically written)
RDFN
(automatically written)
RDFN
(automatically written)
64 bytes 64 bytes
22 bytes
Figure 20.15 EP1 RDFN Operation